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Integrated Circuit Systems, Inc.
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
FEATURES
20 LVCMOS outputs, 7 typical output impedance Output frequency up to 250 MHz 250ps bank skew, 300ps output skew, 350ps multiple frequency skew, 700ps part-to-part skew Selectable inverting and non-inverting outputs LVCMOS / LVTTL clock input LVCMOS / LVTTL control inputs Bank enable logic allows unused banks to be disabled in reduced fanout applications 3.3V or mixed 3.3V input, 2.5V output operating supply modes 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch 0C to 70C ambient operating temperature Other divide values available on request
The ICS8701-01 is a low skew, /1, /2 Clock Generator and a member of the HiPerClockS HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
GENERAL DESCRIPTION
,&6
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset/ output enable input, nMR/OE, resets the internal dividers and controls the active and high impedance states of all outputs. The output polarity inputs, INV0:1, control the polarity (inverting or non-inverting) of the outputs of each bank. Outputs QA0-QA4 are inverting for every combination of the INV0:1 input. The timing relationship between the inverting and noninverting outputs at different frequencies is shown in the Timing Diagrams. The ICS8701-01 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
/1
1 0
PIN ASSIGNMENT
GND QB2 GND QB3 VDDOB QB4 QC0 VDDOC QC1 GND QC2 GND
LVCMOS_CLK DIV_SELA
/2
QAO - QA4 QC3 VDDOC QC4 QD0 VDDOD QD1 GND QD2 GND QD3 VDDOD QD4
1 0
QB0 - QB4
DIV_SELB
1 0
QC0 - QC4
DIV_SELC
1 0
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8701-01
QB1 VDDOB QB0 QA4 VDDOA QA3 GND QA2 GND QA1 VDDOA QA0
DIV_SELD nMR/OE INV0 INV1 Output Polarity Control
DIV_SELA DIV_SELB LVCMOS_CLK GND VDDI INV0 GND INV1 VDDI nMR/OE DIV_SELC DIV_SELD
48-Pin LQFP Y Package Top View
8701-01
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1
REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number 2, 44 5, 11 26, 32 35, 41 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 13 14 23 24 17, 19 15 Name VDDOC VDDOD VDDOA VDDOB GND VDDI QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 LVCMOS_CLK DIV_SELD DIV_SELC DIV_SELB DIV_SELA INV1, INV0 nMR/OE Pow er Pow er Pow er Pow er Pow er Pow er Output Output Output Output Input Input Input Input Input Input Input Pullup Pullup Pullup Pullup Pullup Pullup Pullup Ty pe
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
Description Output Bank C pow er supply. Connect to 3.3V or 2.5V. Output Bank D pow er supply. Connect to 3.3V or 2.5V. Output Bank C pow er supply. Connect to 3.3V or 2.5V. Output Bank B pow er supply. Connect to 3.3V or 2.5V. Ground. Connect to ground. Input pow er supply. Connect to 3.3V. Bank A outputs. LVCMOS interface levels. 7 typical output impedance. Bank B outputs. LVCMOS interface levels. 7 typical output impedance. Bank C outputs. LVCMOS interface levels. 7 typical output impedance. Bank D outputs. LVCMOS interface levels. 7 typical output impedance. Clock input. LVCMOS interface levels. Controls frequency division for bank D outputs. LVCMOS interface levels. Controls frequency division for bank C outputs. LVCMOS interface levels. Controls frequency division for bank B outputs. LVCMOS interface levels. Controls frequency division for bank A outputs. LVCMOS interface levels. Determines polarity of outputs by banks. LVCMOS interface levels. Master reset and output enable. Resets non-inverting outputs to LOW. Sets inverting outputs to HIGH. Enables and disables all outputs. LVCMOS interface levels.
TABLE 2. PIN CHARACTERISTICS
Sy mbol CIN RPULLUP CPD ROUT Parameter Input Capacitance Input Pullup Resistor Pow er Dissipation Capacitance (per output) Output Impedance VDDI, VDDOx = 3.465V VDDI = 3.465V, VDDOx = 2.625V 7 51 Test Conditions Minimum Ty pical Maximum Units pF K pF pF
TABLE 3. FUNCTION TABLE
Inputs nMR/OE 0 1 1 1 1 1 1 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 INV1 X 0 0 1 1 0 0 1 1 INV0 X 0 1 0 1 0 1 0 1 BANK A Hi Z Inverting Inverting Inverting Inverting Inverting Inverting Inverting Inverting BANK B Hi Z Non-inverting Inverting Inverting Inverting Non-inverting Inverting Inverting Inverting Outputs BANK C Hi Z Non-inverting Non-inverting Inverting Inverting Non-inverting Non-inverting Inverting Inverting BANK D Hi Z Non-inverting Non-inverting Non-inverting Inverting Non-inverting Non-inverting Non-inverting Inverting Qx frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
8701-01
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2
REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 4.6V
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
-0.5V to VDDI + 0.5V -0.5V to VDDOx + 0.5V 0C to 70C -65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI = VDDOX = 3.3V5%, TA = 0C TO 70C
Sy mbol VDDI VDDOx VIH VIL IIH IIL IDD VOH VOL Parameter Input Pow er Supply Voltage Output Pow er Supply Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Quiescent Pow er Supply Current Output High Voltage Output Low Voltage VDDOx = 3.135V IOH = -36mA VDDOx =3.135V IOL = 36mA 2.6 0.5 All except LVCMOS_CLK LVCMOS_CLK All except LVCMOS_CLK LVCMOS_CLK VDDI = 3.465V VDDI = 3.135V VDDI = VIN = 3.465V VDDI = VIN = 0V -150 70 Test Conditions Minimum 3.135 3.135 2 2 -0.3 -0.3 Ty pical 3.3 3.3 Maximum 3.465 3.465 3.765 3.765 0.8 1.3 5 Units V V V V V V A A mA V V
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDOX = 3.3V5%, TA=0C TO 70C
Sy mbol fMAX tpLH tpHL tsk(b) tsk(o) tsk() tsk(pp) tR tF tPW tEN Parameter Test Conditions Maximum Input Frequency Propagation Delay, Low -to-High Propagation Delay, High-to-Low Bank Skew ; NOTE 2 Output Skew ; NOTE 3 Multiple Frequency Skew ; NOTE 4 Part to Part Skew ; NOTE 5 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Output Enable Time; NOTE 6 0MHZ < f < 200MHz f = 200MHz 0MHZ < f 200MHz 0MHZ < f 200MHz Measured on falling edge at VDDOx/2 Measured on falling edge at VDDOx/2 Measured on falling edge at VDDOx/2 Measured on falling edge at VDDOx/2
Minimum 2.5 2.5
Ty pical
Maximum 250 3.5 3.5 250 300 350 700
Units MHz ns ns ps ps ps ps ps ps ns ns ns
150 150 tCY CLE/2 - 0.5 2 tCY CLE/2 2.5
700 700 tCY CLE/2 + 0.5 3 6
tDIS Output Disable Time; NOTE 6 6 ns NOTE 1: All parameters measured at 200MHz unless noted otherw ise. All outputs terminated w ith 50 to VDDOx/2. NOTE 2: Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions. NOTE 3: Defined as skew across banks of outputs sw itching in the same direction at the same supply voltages and w ith equal load conditions. NOTE 4: Defined as skew across banks of outputs sw itching in the same direction operating at different frequencies w ith the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at different outputs sw itching in the same direction on different devices operating at the same supply voltages and w ith equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701-01
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3
REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
Test Conditions Minimum 3.135 2.375 VDDI = 3.465V VDDI = 3.135V VDDI = VIN = 3.465V VDDI = VIN = 0V VDDI = 3.135V VDDOx = 2.375V IOH = -27mA VDDI =3.135V VDDOx = 2.375V IOL = 27mA -150 70 1.8 0.5 2 2 -0.3 -0.3 Ty pical 3.3 2.5 Maximum 3.465 2.625 3.765 3.765 0.8 1.3 5 Units V V V V V V A A mA V V
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI = 3.3V5%, VDDOX = 2.5V5%, TA = 0C TO 70C
Sy mbol VDDI VDDOx VIH VIL IIH IIL IDD VOH VOL Parameter Input Pow er Supply Voltage Output Pow er Supply Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Quiescent Pow er Supply Current Output High Voltage Output Low Voltage All except LVCMOS_CLK LVCMOS_CLK All except LVCMOS_CLK LVCMOS_CLK
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VD DI = 3.3V5%, VDDO = 2.5V5%, T A = 0C TO 70C
Sy mbol fMAX tpLH tpHL tsk(b) tsk(o) tsk() tsk(pp) tR tF tPW tEN Parameter Maximum Input Frequency Propagation Delay, Low -to-High Propagation Delay, High-to-Low Bank Skew ; NOTE 2 Output Skew ; NOTE 3 Multiple Frequency Skew ; NOTE 4 Part to Part Skew ; NOTE 5 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width Output Enable Time; NOTE 6 0MHZ < f < 200MHz f = 200MHz 0MHZ < f 200MHz 0MHZ < f 200MHz Measured on falling edge at VDDOx/2 Measured on falling edge at VDDOx/2 Measured on falling edge at VDDOx/2 Measured on falling edge at VDDOx/2 150 150 tCY CLE/2 - 0.5 2 tCY CLE/2 2.5 2.5 2.5 Test Conditions Minimum Ty pical Maximum 250 3.5 3.5 300 300 350 700 720 720 tCY CLE/2 + 0.5 3 6 Units MHz ns ns ps ps ps ps ps ps ns ns ns
tDIS Output Disable Time; NOTE 6 6 ns NOTE 1: All parameters measured at 200MHz unless noted otherw ise. All outputs terminated w ith 50 to VDDOx/2. NOTE 2: Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions. NOTE 3: Defined as skew across banks of outputs sw itching in the same direction at the same supply voltages and w ith equal load conditions. NOTE 4: Defined as skew across banks of outputs sw itching in the same direction operating at different frequency w ith the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at different outputs sw itching in the same direction on different devices operating at the same supply voltages and w ith equal load conditions. NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701-01
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4
REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
FIGURE 1A, 1B - TIMING DIAGRAMS
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
LVCMOS_CLK
QA, /1, INV
QB, /2, INV
QC, /2, NINV
QD, /1, NINV FIGURE 1A - ACTIVE, /1, /2, INVERTING AND NON-INVERTING
nMR/OE
LVCMOS_CLK
QA, /1, INV
QB, /2, INV
QC, /2, NINV
QD, /1, NINV High Impedance Active
FIGURE 1B - RESET TO ACTIVE, /1, /2, INVERTING AND NON-INVERTING
8701-01
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REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK 3.3V VDDI/2
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
VDDI/2
0V tPHL Q tPLH
VDDI/2
VDDI/2
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
nMR/OE
3.3V
VDDI/2 0V tPHZ Q VOH VOH - 300mV
VDDI/2
tPZH
VDDO/2 tPLZ VDDO/2 VOL + 300mV tPZL
Q
VOL
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8701-01
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REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
FIGURE 3A, 3B- SKEW DEFINITIONS & WAVEFORMS
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
Bank Skew - Skew within a bank of outputs at the same supply voltages and with equal load conditions.
CLK
VDDO/2 Qx0 tsk(b)
VDDO/2
tsk(b)

VDDO/2
VDDO/2
Qx4
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew across banks of outputs switching in the same direction at the same supply voltages and with equal load conditions.
CLK
VDDO/2
VDDO/2
QA0 - QA4
tsk(o)
tsk(o)
VDDO/2
VDDO/2
QB0 - QB4 QC0 - QC4 QD0 - QD4
FIGURE 3B - INVERTING OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps www.icst.com
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REV. A - AUGUST 28, 2000
8701-01
Integrated Circuit Systems, Inc.
FIGURE 3C, 3D- SKEW DEFINITIONS & WAVEFORMS
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
Multiple Frequency Skew - Skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions.
CLK QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in /1, inverting tsk(w) QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in /2, inverting
VDDO/2
VDDO/2
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Part to Part Skew - Skew at different outputs switching in the same direction on different devices operating at the same supply voltages and with equal load conditions.
CLK PART 1 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 inverting
VDDO/2
VDDO/2
tsk(p) PART 2 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 inverting
tsk(p)
VDDO/2
VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701-01
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REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
NOTE 4 D NOTE 5, 7 D1 D/2 NOTE 3 -DD1/2
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
e /2
-A, B, OR -D-
b NOTE 3 -ANOTE 3 -BE1 e N O T E 5, 7 N/4 T IPS 0.20 C A-B D E/2 E1/2 E N O T E 4 -A, B, OR -D-
4X
SEE DETAIL "A"
8 PLACES 11 / 13
A
-H- NOT E 2 / / 0.10 C ccc -CSEE DETAIL "B"
NOTES: 1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI Y14.5-1982 2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM PLANE -H- . 4. TO BE DETERMINED AT SEATING PLACE -C- . 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. 6. "N" IS THE TOTAL NUMBER OF TERMINALS. 7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE -H-. 8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG BOTTOM OF PACKAGE. 9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 10. CONTROLLING DIMENSION: MILLIMETER. 11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95 REGISTRATION MS-026, VARIATION BBC. 12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE.
NOTE 9 b
ddd M C A-B S D S WIT H LEAD FINISH
0.09 / 0.20
0.09 / 0.16
S Y M B O L A
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBC MIN. NOM. MAX. 1.60 0.05 1.35 1.40 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.45 0.60 48 0.5 BSC. 0.17 0.17 0.22 0.20 0.27 0.23 0.08 0.08 0.75 0.15 1.45
N O T E
b1 BASE METAL
A1 A2 D D1
12
4 7, 8 4 7, 8
0 MIN. - 0.05 S A2 DATUM PLANE -H0.08/0.20 R. 0.25 GAUGE PLANE
E E1 L N e
A1
0.08 R. MIN. 0.20 MIN. 1.00 REF.
b 0 - 7 L b1 ccc ddd
9
8701-01
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9
REV. A - AUGUST 28, 2000
Integrated Circuit Systems, Inc.
ORDERING INFORMATION
Part/Order Number ICS8701-01Y ICS8701-01Y T Marking ICS8701-01 ICS8701-01
ICS8701-01 LOW SKEW 1, 2 CLOCK GENERATOR W/POLARITY CONTROL
Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 2000 Temperature 0C to 70C 0C to 70C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701-01
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REV. A - AUGUST 28, 2000

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